1. Field of the Invention
This invention relates to testing of electronic circuits, and more particularly, to the testing of integrated circuits having embedded memories.
2. Description of the Related Art
Scan testing is a means of testing the internal logic of large, complex integrated circuits. Test stimulus data is loaded into the integrated circuit via a chain of scannable storage devices (e.g., scan flip flops). A scan chain may be thought of as a long shift register made up of scan devices.
The test stimulus data is then applied by the devices of the scan chain to the internal logic. After allowing time for the logic to respond, result data is captured into devices of the scan chain, after which it may be scanned out for observation and a determination of whether or not the device under test passed.
Many integrated circuits include one or more embedded memories. For example, a microprocessor typically includes at least one cache and at least one register file. Modern microprocessors often include two or levels of cache memory (divided between instructions and data) as well as large register files that allow for the storage of several different register states. These embedded memories are typically not scan testable. Furthermore, embedded memories can often times interfere with test access to certain logic circuits. Because of this, some logic circuits may be untested. Alternatively, a significant amount of extra circuitry may be required to arrange such logic circuits for test access.